1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a thin film transistor and a method for fabricating the same, in which a channel width of the thin film transistor is made greater in a narrow area for improving an on/off performance of the thin film transistor.
2. Background of the Related Art
In general, the thin film transistor is used in place of a CMOS load transistor or a load resistor in an SRAM of 4M or 16M class or over, and also as a switching device for switching a video data signal from each pixel region in a liquid crystal display. Especially, as a PMOS thin film transistor(TFT) is used as a load transistor in the SRAM cell, an off-current in the load transistor can be reduced and an on-current in the load transistor can be increased, to reduce a power consumption in the SRAM cell and to improve a memory characteristic, allowing to obtain a high quality SRAM cell.
A background art thin film transistor and a method for fabricating the same will be explained with reference to the attached drawings. FIG. 1 illustrates a section of the background art thin film transistor.
Referring to FIG. 1, the background art thin film transistor is provided with an insulating layer 21, a gate electrode 22a on the insulating layer 21, a gate insulating film 24 formed on the insulating layer 21 inclusive of the gate electrode 22a, a drain electrode D formed on the gate insulating film 24 spaced apart from the gate electrode 22a, a source electrode S formed on the gate insulating film 24 opposite to the drain electrode D overlapped with the gate electrode 22a, and a channel region I and an offset region II formed on the gate insulating film 24 between the source electrode S and the drain electrode D. The offset region II is a region between the drain electrode D and the gate electrode 22a.
A background art method for fabricating a thin film transistor will be explained. FIGS. 2A.about.2D illustrates sections showing the process steps of the background art method for fabricating a thin film transistor.
Referring to FIG. 2A, a first polysilicon layer 22 to be used as a gate electrode of a bulk transistor is formed on an insulating layer 21. Photoresist is coated on the first polysilicon layer 22 and exposed and developed to form a mask pattern 23. The first polysilicon layer 22 is selectively etched using the mask pattern 23, to form a gate electrode 22a as shown in FIG. 2B. Then, as shown in FIG. 2C, a gate insulating film 24 is deposited on the insulating layer 21 inclusive of the gate electrode 22a. A second polysilicon layer 25 to be used as source and drain electrodes, an offset region and a channel region is formed on the gate insulating film 24. A photoresist 26 is coated on the second polysilicon layer 25 and patterned by exposure and development. As shown in FIG. 2D, the patterned photoresist 26a defines the channel region and the offset region. Then, impurity ions are injected into the exposed second polysilicon layer 25 using the patterned photoresist 26a as a mask, to form source/drain. Accordingly, the source electrode S is formed overlapped with a portion of the gate electrode 22a, and the drain electrode D is formed spaced from the gate electrode 22a. And, the channel region I and the offset region II are formed between the source electrode S and the drain electrode D.
However, the background art thin film transistor and the method for fabricating the same has a problem in that it has a lower on-current because the offset region is not influenced from a gate voltage.